An Iteration Control Algorithm for Multi-Rate Layered LDPC Decoder
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 99 === Iteration control is an important issue for the iterative decoding of LDPC codes since it can tremendously increase the decoding throughput or reduce the power consumption. In this thesis, we proposed an iteration control algorithm for the multi-rate layered dec...
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| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/62100135093591948434 |
| Summary: | 碩士 === 國立臺灣大學 === 資訊工程學研究所 === 99 === Iteration control is an important issue for the iterative decoding of LDPC codes since it can tremendously increase the decoding throughput or reduce the power consumption. In this thesis, we proposed an iteration control algorithm for the multi-rate layered decoder. Our iteration control algorithm introduces no bit error rate (BER) degradation in successful decoding detection. For unsuccessful decoding, we proposed a low computation complexity decision metric for early detect undecodable blocks. Simulation results show that our proposed algorithm can significantly reduce average number of decoding iterations while maintains the BER performance. Partially parallel characteristic of proposed algorithm makes it easily integrated into multi-rate layered LDPC decoder. The FPGA implementation results show that our architecture only add 1.0% hardware cost to a 32-thread multi-rate layered decoder.
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