| Summary: | 碩士 === 國立臺灣大學 === 材料科學與工程學研究所 === 99 === Progression over time, electronic products developed to be multi-function and ultra-portable. Hence, the ICs’(Integrated Circuits) configuration also according to the roadmap of ITRS(The International Technology Roadmap for Semiconductors), researching institutes and companies are developing cutting-edge IC producing technologies, that makes number of transistor on each IC to steps up. Meanwhile, because of multi-function of the chips, that needs to raise the I/O counts, so flip-chip package technology becomes the candidate that packaging these advancing chips. Especially for high-I/O counts chips like CPUs(Central Process Unit), GPUs(Graphic Process Unit) and DRAMs(Dynamic Random Access Memory).
According to the ITRS 2010 edition, bump pitch of first level package will shrink down from 50 micron to 40 micron in 2012 by 2 years, and 35 micron at 2016. Under such nearing bump pitch, bump diameter should be closer than bump pitch, accompanying electromigration effect under ultra-high current density.
Formers discussed electromigration effect in solder joint, most of them used constant current density and constant environment temperature. But, for conducting chips, Joule heating effect will raise the temperature and higher than environment temperature, especially under ultra-high current density condition. We know in lead-free solder systems, the melting points are around 220 degree Celsius, and no matter with Cu or Ni UBM, solid state chemical reaction will occur to form IMCs(Intelmetallic Compounds) under 100 degree Celsius, this outcome altering the solder-bump microstructure and texture. Hence not only the conducting current varying solder-bump system, but also the temperature, too.
In order to cancel out the influence of Joule heating effect, the experimental uses oil-cooling system as a heat sink, reducing the chip temperature to 50 degree Celsius and applied with ultra-high current density of 105 Ampere per square centimeter. Tests were conducted with 400, 800, 1200, 1600 and 2000 hour. The bump pitch is 20 micron and the bump diameter is 12 micron. The bump configuration before face-to-face bonding is Al(8kA)/Cu(5μm)/Ni(3μm)/Sn-2.5Ag(5μm). After the test, chips was cold-mounted, grinded and polished. Examined bump microstructure by SEM(Scanning Electron Microscope) and specified phase composition by EDS(Energy-dispersive X-Ray Spectroscopy).
Even though the ultra-high current density was conducted, the daisy chain on chip can still carry current after 2000 hours test. This result confirmed by resistance measuring. The resistance increment ratio was 44%.
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