| Summary: | 碩士 === 國立臺灣海洋大學 === 資訊工程學系 === 99 === With the ever increasing needs of pipelined processors in recent years, how to improve the accuracy of branch predictor has become an important issue. In this thesis, we analyze and empirically study the variable history length branch predictor schemes for modern processors. Based on SimpleScalar/Wattch simulators and SPEC2000 benchmarks, we study and compare the performance, critical path delay, hardware cost and power consumption for prediction methods using Fast Path-Based Neural Branch Predictor (FPB), Piecewise Linear Branch Predictor (PLB) and TAgged GEometric history length Branch Predictor (TAGE) as well as Optimized GEometric History Length branch predictor (O-GEHL).
Based on these empirical studies, we propose an improving TAgged GEometric history length Branch predictor variant, f-TAGE (fast TAGE). f-TAGE not only preserves branch prediction accuracy but also reduces critical path delay up to 20% at the cost of modest hardware increase less than 1%.
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