Investigation and application of the performance of the SOI MOSFET

• Main Authors: Tzu-yun Chiu, 邱子芸
• Other Authors: Chu-Yu Chen
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/28125107575244734719

碩士 === 國立臺南大學 === 通訊工程研究所碩士班 === 99 === In this paper we propose the SOI(Silicon-on-Insulator) MOSFET structure to can improve the undesirable effects in the size reduction process of the Bulk MOSFET devices. In this structure, the parasitic capacitance resulted from the source and drain PN junction has been significantly reduced. And the short channel effect which results in the dropping of the threshold voltage can be effectively improved. Also, Leakage current due to tunneling effect can also be effectively suppressed. In the study of the high-voltage ESD protection, the breakdown voltage and the snapback breakdown voltage can be used to evaluate the reliability of devices. It can be further verified that the breakdown voltage at the snapback breakdown voltage are affected by the channel length of the N-well and P-body. Simulation results show snapback breakdown voltage with lower holding voltage characteristic may cause Latch-up problem. The characteristics of SOI MOSFET structure are proved to be an effective technique for improving the Latch-up problem.