A Novel Low Gate-Count Pipelined Serializer Topology with Multiplexer-Flip-Flops
碩士 === 國立清華大學 === 電機工程學系 === 99 === This paper proposes a pipelined serializer topology with MUX-FFs to be a high-throughput and low-cost solution for serial link interface transmitters. Analysis and simulation results show that the serializer in proposed topology reduces 52% the gate count without...
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2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33345964711978102596 |
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ndltd-TW-099NTHU54420932015-10-13T20:23:01Z http://ndltd.ncl.edu.tw/handle/33345964711978102596 A Novel Low Gate-Count Pipelined Serializer Topology with Multiplexer-Flip-Flops 一個新穎的低邏輯閘數管線化序列產生器架構採用多功正反器 Tsai, Wei-Yu 蔡維祐 碩士 國立清華大學 電機工程學系 99 This paper proposes a pipelined serializer topology with MUX-FFs to be a high-throughput and low-cost solution for serial link interface transmitters. Analysis and simulation results show that the serializer in proposed topology reduces 52% the gate count without slowing down the serializer. To verify the functions of the proposed design, two chips are implemented with the 4-to-1 MUX-FF and proposed 8-to-1 serializer in 90 nm CMOS technology. The measured results shows that the MUX-FF and the proposed serializer with MUX-FFs are bit-error-free (with BER < 10^-12), operate at up to 6 Gbits/s and 12 Gbit/s, respectively. Hsu, Yarsun Chiu, Ching-Te 許雅三 邱瀞德 2011 學位論文 ; thesis 30 en_US |
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NDLTD |
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en_US |
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Others
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NDLTD |
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碩士 === 國立清華大學 === 電機工程學系 === 99 === This paper proposes a pipelined serializer topology with MUX-FFs to be a high-throughput and low-cost solution for serial link interface transmitters. Analysis and simulation results show that the serializer in proposed topology reduces 52% the gate count without slowing down the serializer. To verify the functions of the proposed design, two chips are implemented with the 4-to-1 MUX-FF and proposed 8-to-1 serializer in 90 nm CMOS technology. The measured results shows that the MUX-FF and the proposed serializer with MUX-FFs are bit-error-free (with BER < 10^-12), operate at up to 6 Gbits/s and 12 Gbit/s, respectively.
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| author2 |
Hsu, Yarsun |
| author_facet |
Hsu, Yarsun Tsai, Wei-Yu 蔡維祐 |
| author |
Tsai, Wei-Yu 蔡維祐 |
| spellingShingle |
Tsai, Wei-Yu 蔡維祐 A Novel Low Gate-Count Pipelined Serializer Topology with Multiplexer-Flip-Flops |
| author_sort |
Tsai, Wei-Yu |
| title |
A Novel Low Gate-Count Pipelined Serializer Topology with Multiplexer-Flip-Flops |
| title_short |
A Novel Low Gate-Count Pipelined Serializer Topology with Multiplexer-Flip-Flops |
| title_full |
A Novel Low Gate-Count Pipelined Serializer Topology with Multiplexer-Flip-Flops |
| title_fullStr |
A Novel Low Gate-Count Pipelined Serializer Topology with Multiplexer-Flip-Flops |
| title_full_unstemmed |
A Novel Low Gate-Count Pipelined Serializer Topology with Multiplexer-Flip-Flops |
| title_sort |
novel low gate-count pipelined serializer topology with multiplexer-flip-flops |
| publishDate |
2011 |
| url |
http://ndltd.ncl.edu.tw/handle/33345964711978102596 |
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