A Novel Low Gate-Count Pipelined Serializer Topology with Multiplexer-Flip-Flops
碩士 === 國立清華大學 === 電機工程學系 === 99 === This paper proposes a pipelined serializer topology with MUX-FFs to be a high-throughput and low-cost solution for serial link interface transmitters. Analysis and simulation results show that the serializer in proposed topology reduces 52% the gate count without...
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| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33345964711978102596 |
| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 99 === This paper proposes a pipelined serializer topology with MUX-FFs to be a high-throughput and low-cost solution for serial link interface transmitters. Analysis and simulation results show that the serializer in proposed topology reduces 52% the gate count without slowing down the serializer. To verify the functions of the proposed design, two chips are implemented with the 4-to-1 MUX-FF and proposed 8-to-1 serializer in 90 nm CMOS technology. The measured results shows that the MUX-FF and the proposed serializer with MUX-FFs are bit-error-free (with BER < 10^-12), operate at up to 6 Gbits/s and 12 Gbit/s, respectively.
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