Design and Implementation of a High Performance Closed-Loop MIMO Communications with Ultra Low Complexity Handset

• Main Authors: Yuan, Yu-Han, 袁鈺涵
• Other Authors: Ma, Hsi-Pin
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/12274293481756564674

碩士 === 國立清華大學 === 電機工程學系 === 99 === In this thesis, specification study, system simulation, architecture design and logic design along with SoC platform implementation of a high performance closed-loop MIMO communications with ultra low complexity handset is presented. In order to provide the better link quality and/or increase the transmission data rate in communications, MIMO techniques are applied in the communication systems. Recently, the channel state information (CSI) may be gathered by the transmitter itself exploiting channel reciprocity in time-division duplex (TDD) systems. It has attracted considerable attention since that can achieves better performance than conventional ones. Several types of closed-loop MIMO systems for wireless communication are discussed and the related MIMO transceiver design based on Geometric Mean Decomposition are also introduced. This thesis proposes an efficient and practicable MIMO transceiver in which transmitter antenna selection is applied to geometric mean decomposition (GMD) which is combined with Tomlinson-Harashima Precoding (THP) in TDD system. This work enhances the conventional GMD-THP and compensates the deficiency of the algorithm under ill-conditioned channel in TDD system. From the floating-point simulation results, the proposed transceiver can achieve about 7 dB SNR improvement over the open-loop VBLAST counterparts at BER=10^(-2) under i.i.d. channel. Moreover, we analyze the computation complexity with various Tx antenna selection (T-AS) configuration for 0.1dB gain improvement. From the analysis result, we can decide that 4 x 6 transmitter antenna selection is the best choose. Simulations are based on the MIMO fading channel model with white noise. The elements in the channel matrix are assumed i.i.d. complex Gaussian random variable with zero mean and variance of 0.5 per dimension. Simulations are under flat fading and quasi-stationary environment. In view of hardware complexity, some modified schemes and hardware simplifications are presented to save the VLSI design cost. In order to save the GMD computation at the handset, we also take the decoder quantization/reconstruction into consideration. Make use of a little bandwidth, we just send the needed decoder codewords to the handset. Then, it can be simple for the handset. Because of quantized decoder, we must do some modifications to GMD-THP. The proposed work can save more than 60% computational complexity at the handset compared with that of the GMD scheme is comparable to the conventional linear transceiver schemes. In the hardware design, most of all the functional block is fully implemented while except for SVD part. Since there are many approaches to the SVD and it is not our main contribution to implement it. The total equivalent gate count of proposed work at the handset is 109,101. The hardware cost of the proposed work compared to another transceiver scheme for 4 x 6 transmitter antenna selection (T-AS) can save 60%. Furthermore, if we consider the hardware cost of SVD, it can save more than 60%. The maximum operating clock rate of the transceiver can achieve about 50 MHz and the corresponding maximum throughput is 120 Mbps for 64-QAM in FPGA emulation. Finally, a MIMO joint transceiver is implemented on a SoC platform which is realized to do the hardware/software (HW/SW) co-verification strategy to debug the proposed architecture. In this thesis, which introduces the figure file to be the transmission media. Designer could verify the decoded results in various environment by liquid crystal display (LCD) panel. The maximum operating clock rate of the transceiver can achieve about 10 MHz and the corresponding maximum throughput is 16 Mbps for 16-QAM on SoC platform.