Study of Ultra Shallow Junction Formation for 45 and 65 nm Devices Applications

• Main Authors: Nieh, Chun-Feng, 聶俊峰
• Other Authors: Huang, Chih-Fang
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/18770757375640220972

博士 === 國立清華大學 === 電子工程研究所 === 99 === As CMOS technology continue to scale down, dopant profile engineering has become one of the major technology challenged in CMOS device fabrication. In the aggressively scaled CMOS device, shallow p-n junctions and low sheet resistances are essential for short channel effect (SCE) control and high device performance. Conventionally, low-energy ion implantation and the spike anneal are utilized to form ultra shallow junction (USJ) in CMOS fabrication. This dissertation addresses the investigation of implantation damage induced anomalous diffusion by effective co-implant profile design and thermal sequence optimization of millisecond anneal which successfully demonstrates in scaled CMOS device. First, we have studied the interactions between implant defects and phosphorus diffusion in crystalline silicon. Defect engineering enables ultra shallow n+/p junction formation by using phosphorus, carbon and germanium co-implants, and spike anneal. The resultant phosphorus junction depth is less tan 20 nm comparing 46 nm without co-implants at phosphorus concentration of 5x1015 cm-3. Our experimental data suggest that the positioning of a preamorphized layer using germanium implants plays an important role in phosphorus diffusion. We find that extending the overlap of germanium preamorphization and carbon profiles results in greater reduction of phosphorus transient-enhanced diffusion (TED) by trapping more excess interstitials This conclusion is consistent with the end-of-range (EOR) defects calculated by Monte Carlos simulation and annealed carbon profiles. Our results also proved useful insight into the ultra shallow junction formation in aggressively scaled CMOS technology. Second, we present an alternative approach to achieve ultra shallow junction formation using carbon co-implant in the sub-65 nm PMOS devices in which the notorious boron interstitial diffusion is greatly retarded. Carbon co-implant is used in conjunction with boron implants in the source/drain extension (SDE) aiming at short channel effect improvement. Upon process optimization, 26 mV (20% improvement) drain induced barrier lowering (DIBL) improvement can be obtained. We also describe our efforts to circumvent the inevitable junction leakage during the co-implant process by source/drain extension implant profile re-engineering. Meanwhile, we present a new approach to achieve superior short channel effect control in the embedded SiGe p-MOSFET devices using tilted co-implant, in which resulting in greatly improved short channel effect and preventing implant induced strained relaxation problem. By this new approach, 5 % p-MOSFET Idsat improvement is demonstrated in sub-45nm node device. In addition, we demonstrate co-implant enhanced junction leakage current suppression by 1-2 orders of magnitude due to modifications of SiGe surface morphology in the presence of co-implant, where silicide spiking possibility during the silicidation process is greatly reduced, preventing junction leakage. Finally, we have studied the effects of the millisecond anneal in conjunction with conventional spike anneal on the p-n junction formation in CMOS devices. Our results reveal that the millisecond and spike anneal sequence plays an important role in the implanted boron p+/n junction formation. On blanket silicon wafers, the millisecond anneal followed by the spike anneal increases implanted boron solid solubility in crystalline silicon by ~18% compared to that obtained using reversed annealing sequence under the same annealing conditions. This result substantially alters the short channel effect behavior in the fabricated CMOS devices, resulting in opposite threshold voltage behaviors in PMOS and NMOS devices when using boron as NMOS halo implant. Our results also provide useful insights into ultra shallow junction formation and short channel effect control when scaling CMOS technology.