| Summary: | 博士 === 國立清華大學 === 電子工程研究所 === 99 === As the gate length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is of the order of nanometers, it is very difficult to maintain their electrical properties with the different species, accelerated energy and implant dosage. In this thesis, we study the effects of surface-charge on MOSFETs devices by a positive ion-implanted beam accompanying an electron-beam current for surface-charge neutralization. Without or insufficient for the negative electron-beam current, films show a higher sheet resistance, a lower threshold voltage, breakdown voltage, and gain factor. If the electron-beam current is equal to or higher than the ion-beam current, the uniformity of sheet-resistance and the fluctuations of breakdown voltage and gain factor will be significantly improved by controlling the charge neutralization. It will prevent the positive ion charges from penetrating through the poly-gate to cause the catastrophic damages in the gate-oxide layer.The effects of arsenic-ion implanted beam density on defect evolution in photoresist and polysilicon film also have been investigated. The ion implantation by heavy ions, such as arsenic ions, would induce an elevated temperature and positive charge accumulation on the photoresist film and polysilicon surface at a high implanted beam density, due to the accelerated energy transfer into the implanted amorphous area. The popping generation upon the photoresist film at a higher surface elevated temperature and the polysilicon resistance linearly increases with the implanted-ion beam density after a subsequent annealing process. Therefore, by optimizing the ion beam density, the surface temperature and charge accumulated potential would be reduced and well-controlled to obtain a stable polysilicon sheet resistance at the role of gate electrode.In this thesis, we also study the influence in the nano-scale gate length of pMOSFETs technology using germanium preamorphization implantation (Ge PAI). It is demonstrated that the channeling can be eliminated and minimize the short channel effect by the formation of a Ge-implantation induced thin amorphous layer near the surface prior to boron implantation. Optimizing the amorphous layer thickness by controlling a high 72Ge/74Ge ratio, the device performance of pMOSFETs can be enhanced. It is also found that the thin Ge PAI amorphous layer formed by a low 72Ge/74Ge ratio would cause the degradation of threshold voltage (Vth) roll-off characteristics and Ion/Ioff ratio, as compared to that formed by a high 72Ge/74Ge ratio. It is attributed to a thinner Ge amorphous layer that has a weak ability to suppress the tail of boron ions, as compared to a thicker Ge amorphous layer at the same implanted doses and energies among various 72Ge/74Ge ratios.
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