Analysis and Modeling of Edge Effect on Inter-Poly Dielectric Layer of Floating Gate Flash Memory

• Main Authors: Wu, Tung-Han, 吳東翰
• Other Authors: Lien, Chen-Hsin
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/29512279502310702623

碩士 === 國立清華大學 === 電子工程研究所 === 99 === The “edge effect” means that edge of oxide would be abnormal after performing high temperature process, and the efficiency of device will degrade. Edge effect on inter-poly dielectric (IPD) layer of floating gate flash memory occurs when re-oxidation restores the damage of edge of IPD layer which is due to defining gate pattern of floating gate flash memory, re-oxidation would lead to thickening of oxide edge, and program speed of memory will become lower. The contribution of this thesis is to propose a model which can analyze edge effect on inter-poly dielectric (IPD) layer of floating gate flash memory and compare them to the edge effect on tunneling oxide. Simulation by MEDICI and proposed model shows that when IPD edge thickens 6nm, memory window reduces 0.3-0.9V; when tunneling oxide edge thickens 2nm, memory window reduces 0.1-2.2V, it shows that program speed variation due to edge effect on tunneling oxide is larger than on IPD layer. Besides, there are two shapes of edge in proposed model: linear edge and parabolic edge. When IPD edge thickens 6nm and edge encroachment is not overlapped, we adopt linear edge to analyze variation of program speed. We find that memory window is 0.2V smaller than the result which is analyzed by parabolic edge, so variation of program speed of linear edge is larger than of parabolic edge when edge encroachment is not overlapped. Thinner edge can increase program speed. The simulation shows that memory window increases 0.5-0.8V when thickness of IPD edge reduces 4nm, but too thinner edge on IPD layer could result in program saturation.