On Synthesis and Optimization of VLSI Designs for Verification
博士 === 國立清華大學 === 資訊工程學系 === 99 === With the growth of design complexity, verification has become one of the primary bottlenecks of the design process. Studies show that verification could take 40% to 70% of the total development effort for the design. As a result, reducing verification time directl...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/00251843612489448700 |