Design and Implementation of a CMOS-MEMS Accelerometer Using Symmetric Layer Stacking Structure
碩士 === 國立清華大學 === 動力機械工程學系 === 99 === This study utilizes TSMC 0.35um Mixed Signal 2P4M Polycide process, combined with proposed post-process to design and fabricate a CMOS-MEMS accelerometer. The merit of this study is that through post-CMOS process with wet, and dry etching to design and fabricate...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67980426382232139427 |