Design of A Novel Mixed-Voltage-Tolerant I/O Buffer with High Reliability

• Main Authors: Hsiao-Han Hou, 侯筱涵
• Other Authors: Chua-Chin Wang
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/93756739148778233314

碩士 === 國立中山大學 === 電機工程學系研究所 === 99 === This thesis is composed of two parts: a 3×VDD mixed-voltage-tolerant I/O buffer with 1×VDD CMOS standard device, and a PVT detector for 2×VDD output buffer with slew-rate compensation. In the first topic, a 3×VDD bidirectional mixed-voltage-tolerant I/O buffer, which has been implemented using a typical TSMC 0.18 μm CMOS process, is proposed with a Dynamic gate bias voltage generator to provide appropriate gate drives for the stacked output stage. Besides, a Gate-tracking circuit and a Floating N-well technique are adopted to prevent 1×VDD device from gate-oxide overstress problems and leakage currents. The maximum data rate is simulated to be 166/166/166/100/80 MHz when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, respectively, given an equivalent probe capacitive load of 10pF. The second topic is a process, voltage, and temperature（PVT）detector for 2×VDD output buffer with slew-rate compensation. The threshold voltage（Vth） of PMOSs and NMOSs varying with process variation could be detected, respectively. In addition, the voltage and temperature variations could be monitored, respectively, by detecting different charging and discharging times of delay buffers at each PVT corner. By adjusting output currents, the slew rate of output signals could be compensated over 24％. Moreover, the maximum data rate with compensation is 133 MHz in contrast with 100 MHz without compensation when VDDIO ＝ 1.8 V, in transmitting mode.