The Digital Delay-Controlled SAR Delay Locked-Loop with Low Power in Sleep Mode
碩士 === 國立中山大學 === 資訊工程學系研究所 === 99 === A successive approximation register (SAR) circuit is adopted to control the digital delay line in the delay-locked loop (DLL) to achieve very fast locking effect in this proposed thesis. And in order to get low power consumption results, a loop state controller...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/68513089046515636785 |