Simulation of 80-nm Symmetric with Asymmetric n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors and Poly-Si Nanowire Transistors

碩士 === 國立東華大學 === 電機工程學系 === 99 === As the metal-oxide-semiconductor field-effect transistors (MOSFETs) keep scaling down, the difficulty and cost of their manufacturing process become higher and the short channel effects (SCEs) get worse. In this paper, we use the commercial semiconductor process a...

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Main Authors:	Yan-Yu Pan, 潘彥瑜
Other Authors:	Keng-Ming Liu
Format:	Others
Language:	zh-TW
Published:	2011
Online Access:	http://ndltd.ncl.edu.tw/handle/20022034744481369624

id	ndltd-TW-099NDHU5442060
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spelling	ndltd-TW-099NDHU54420602015-10-16T04:05:35Z http://ndltd.ncl.edu.tw/handle/20022034744481369624 Simulation of 80-nm Symmetric with Asymmetric n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors and Poly-Si Nanowire Transistors 80奈米對稱與非對稱n型金氧半場效電晶體及多晶矽奈米線電晶體之模擬 Yan-Yu Pan 潘彥瑜碩士國立東華大學電機工程學系 99 As the metal-oxide-semiconductor field-effect transistors (MOSFETs) keep scaling down, the difficulty and cost of their manufacturing process become higher and the short channel effects (SCEs) get worse. In this paper, we use the commercial semiconductor process and device simulator, Sentaurus, to simulate the device characteristics of the 80-nm MOSFETs in order to reduce the cost of developing devices. The device characteristics we investigated include: threshold voltage, subthreshold swing (S.S.), drain-induced barrier lowering (DIBL), and on-off current ratio. First, we simulated the real process flow of the 80-nm MOSFETs by the process simulator and then use the process simulation result as the input of the device simulator. In this work, we simulate both symmetric and asymmetric n-channel MOSFETs. The asymmetric MOSFETs can be manufactured by the double patterning technique. We simulate the double patterning process and the asymmetric halo implant in the source or drain side by the process simulator. The simulated device characteristics of the symmetric and asymmetric n-channel MOSFETs are compared. Also, our simulation results show a good agreement with the experimental data provided by the National Chiao Tung University. We also use 3D process simulation to simulate the Poly-Si nanowire transistors, preliminary discussions electrical components of nanowire transistors. Keng-Ming Liu 劉耿銘 2011 學位論文 ; thesis 63 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立東華大學 === 電機工程學系 === 99 === As the metal-oxide-semiconductor field-effect transistors (MOSFETs) keep scaling down, the difficulty and cost of their manufacturing process become higher and the short channel effects (SCEs) get worse. In this paper, we use the commercial semiconductor process and device simulator, Sentaurus, to simulate the device characteristics of the 80-nm MOSFETs in order to reduce the cost of developing devices. The device characteristics we investigated include: threshold voltage, subthreshold swing (S.S.), drain-induced barrier lowering (DIBL), and on-off current ratio. First, we simulated the real process flow of the 80-nm MOSFETs by the process simulator and then use the process simulation result as the input of the device simulator. In this work, we simulate both symmetric and asymmetric n-channel MOSFETs. The asymmetric MOSFETs can be manufactured by the double patterning technique. We simulate the double patterning process and the asymmetric halo implant in the source or drain side by the process simulator. The simulated device characteristics of the symmetric and asymmetric n-channel MOSFETs are compared. Also, our simulation results show a good agreement with the experimental data provided by the National Chiao Tung University. We also use 3D process simulation to simulate the Poly-Si nanowire transistors, preliminary discussions electrical components of nanowire transistors.
author2	Keng-Ming Liu
author_facet	Keng-Ming Liu Yan-Yu Pan 潘彥瑜
author	Yan-Yu Pan 潘彥瑜
spellingShingle	Yan-Yu Pan 潘彥瑜 Simulation of 80-nm Symmetric with Asymmetric n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors and Poly-Si Nanowire Transistors
author_sort	Yan-Yu Pan
title	Simulation of 80-nm Symmetric with Asymmetric n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors and Poly-Si Nanowire Transistors
title_short	Simulation of 80-nm Symmetric with Asymmetric n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors and Poly-Si Nanowire Transistors
title_full	Simulation of 80-nm Symmetric with Asymmetric n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors and Poly-Si Nanowire Transistors
title_fullStr	Simulation of 80-nm Symmetric with Asymmetric n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors and Poly-Si Nanowire Transistors
title_full_unstemmed	Simulation of 80-nm Symmetric with Asymmetric n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors and Poly-Si Nanowire Transistors
title_sort	simulation of 80-nm symmetric with asymmetric n-channel metal-oxide-semiconductor field-effect transistors and poly-si nanowire transistors
publishDate	2011
url	http://ndltd.ncl.edu.tw/handle/20022034744481369624
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Simulation of 80-nm Symmetric with Asymmetric n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors and Poly-Si Nanowire Transistors

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