| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 99 === As the metal-oxide-semiconductor field-effect transistors (MOSFETs) keep scaling down, the difficulty and cost of their manufacturing process become higher and the short channel effects (SCEs) get worse. In this paper, we use the commercial semiconductor process and device simulator, Sentaurus, to simulate the device characteristics of the 80-nm MOSFETs in order to reduce the cost of developing devices. The device characteristics we investigated include: threshold voltage, subthreshold swing (S.S.), drain-induced barrier lowering (DIBL), and on-off current ratio. First, we simulated the real process flow of the 80-nm MOSFETs by the process simulator and then use the process simulation result as the input of the device simulator. In this work, we simulate both symmetric and asymmetric n-channel MOSFETs. The asymmetric MOSFETs can be manufactured by the double patterning technique. We simulate the double patterning process and the asymmetric halo implant in the source or drain side by the process simulator. The simulated device characteristics of the symmetric and asymmetric n-channel MOSFETs are compared. Also, our simulation results show a good agreement with the experimental data provided by the National Chiao Tung University. We also use 3D process simulation to simulate the Poly-Si nanowire transistors, preliminary discussions electrical components of nanowire transistors.
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