| Summary: | 博士 === 國立彰化師範大學 === 電機工程學系 === 99 === According to the difference in the design structure, the Direct Digital Frequency Synthesizer (DDFS) can be classified into the ROM-base direct digital frequency synthesizer and the ROM-less direct digital frequency synthesizer. The former, due to its larger chip area and memory power consumption, affects the entire DDFS performance, while the latter is criticized by its poor performance of output spectral purity and complex calculations. In order to break the bottleneck of the design, this dissertation presents a new algorithm to design a new DDFS. This algorithm utilizes the symmetry properties of trigonometric functions to image a sinusoidal wave with a phase range of 0 to to the range of 0 to , and then uses the trigonometric function formula incorporated with Taylor’s series and a linear interpolation method to reduce the original ROM of 18-bit to the cosine and tangent functions with a ROM size of 16-bit. Thus, a new algorithm of two-level lookup table can be installed and the ROM area can be decreased under little degradation of the output signals. As compared with other two-level lookup table DDFSs of similar design structure, the required ROM area decreases 32%. In addition, as compared with other not two-level lookup table DDFSs, the DDFS designed in this dissertation has lower power consumption and smaller chip area. Therefore, it is very suitable for wireless communication and portable communication devices. The research results show that this DDFS owns benefits of highspeed frequency transformation, ultrahigh frequency resolution, low phase noise, and low power consumption. Moreover, the phase of the frequency transform is continuous that it can perform direct digital phase and frequency modulation.
This study utilizes the Modelsim development tool and the Verilog hardware-description language, and also applies the devices of Taiwan Semiconductor Manufacturing Company (TSMC) to achieve the development, design, simulation, and analysis of DDFS. The verified results show that under a 3.0-V operation voltage the averaged Spurious-Free Dynamic Range (SFDR) of the designed DDFS achieves 81.2 dBc and the frequency resolution reaches 419.6 Hz with a working frequency up to 110 MHz, while the power consumption is only 68.2 mW. In other words, the averaged power consumption is 0.68 mW per megahertz, which is far less than those of other conventional DDFSs. Therefore, the research result can provide a reference for the future development and applications of DDFS technologies.
Keywords: Direct digital frequency synthesizer, spectrum purity, frequency resolution, read only memory, spurious-free dynamic range.
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