| Summary: | 碩士 === 國立彰化師範大學 === 電子工程學系 === 99 === A code checker plays an important role in dependable computation, reliable communication and error detection for memory, so it can be widely used in digital systems,
calculator system and communication system. Advance of technology, Recent products are asked for low-cost and high efficiency, therefore the area, power consumption and speed has become the most important problem of checker. Additionally, A checker itself may have errors, so whether the checker can self-check is also an important issue.
Constant-Weight Code is the famous Error Detection Codes, and the encoding technology doesn’t needs encoder and checkbit, instead it uses the character of Constant-Weight Code to design. However, traditional checker which is composed of counter needs very big area, so author proposed to use different counter or sorter to make checker.
In this paper we present a novel dependable and high-speed m-out-of-2m code checker with totally self-checking. Additionally, this paper presents architecture can be used in content addressable memory, it can make the data more reliable. Finally, comparing with the latest literature, we can find that it not only needs fewer sorter, T(n) and level, but also can provide the error detection of circuit.
Moreover, this paper is simulating and verifying ours checker which is using the TSMC 1P6M 0.18m polycide technology. Experiment results shows ours checker has high-speed and low power consumption.
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