Design of a Controllable Local Clock Generator for Power Management in GALS Architectures
碩士 === 國立彰化師範大學 === 資訊工程學系 === 99 === Because of the increase in complexity of using a global clock over a single clock chip, globally asynchronous and locally synchronous (GALS) systems are becoming an efficient alternative technique to design system-on-chip (SOC). A single clock chip will reduce f...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/90082164170214497022 |