| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 99 === At present, intelligent surveillance systems attempt to raise amount of high resolution cameras, for achieving on real-time process. Those systems stupendously increase the computational load on central server. For reducing the burden of sever, we propose that let the camera is capable of analyzing information. For total coast reducing, we need to develop a low coast system. This paper proposes a low cost OR1200-based SoC design. The proposed architecture consists of foreground detection accelerator, noise reduction accelerator, object level tracking accelerator and a programmable processor for software development.
In this paper, we propose a method to simplify foreground detection. We utilize the characteristic of video, there are spatial smooth and temporal continuity, to accelerate the foreground detection and reduce memory bandwidth. Compare the computational time of previous work, the experimental result of simulation shows the computational time reduces 61.99% and 56.99% on indoor and outdoor scene separately.
In SoC design, pipelining and parallelizing techniques are largely used to increase the throughput. The total gate count is 128.746K, the total cell area is 653232 mm2 and the operation frequency for real-time HD720p sized sequence processing is 31.7 MHz and 300MHz for accelerators and OR1200 RISC processor respectively.
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