The Implementations on K/V-Band Voltage Controlled Oscillators and V-Band Third Sub-harmonic Injection Locked Oscillator

• Main Authors: Tzu-Yi Lian, 連子誼
• Other Authors: Hwann-Kaeo Chiou
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/60202734869888924387

碩士 === 國立中央大學 === 電機工程研究所 === 99 === This thesis studies two subjects. The first one is the design of voltage control oscillator. Two K-band VCOs and two V-band VCOs were designed and implemented. The second one is the design of injection lock oscillator. A V-band third sub-harmonic injection lock oscillator was implemented. Aforementioned circuits were implemented in tsmcTM 0.18 ?m CMOS, 90 nm CMOS and UMCTM 90 nm CMOS technologies. The thesis is organized as follow, Chapter 1 gives the motivation and induction of system applications. Chapter 2 introduces two K-band VCO topologies which were fabricated in tsmcTM 0.18 ?m CMOS technology. The first circuit is the gate-to-source feedback Coliptts VCO. The proposed gm-boosted technique solves the problem of difficult oscillation of conventional Coliptts VCO. The measured oscillation central frequency is 21.09 GHz with the tunable frequency range from 21.06 to 21.18 GHz. The phase noise is -104.7 dBc/HZ at 1 MHz offset, and the maximum output power is -9.8 dBm. The total power consumption is 24.43 mW. The figure of merit ( FOM ) is -177.3 dBc/Hz. The second circuit continues to improve the gm-boosting ability. The cascode gm-boosted Coliptts VCO is designed. The measured oscillation central frequency is 25.0 GHz with the tunable frequency range from 24.65 to 25.23 GHz. The phase noise is -97.7 dBc/Hz at 1 MHz offset, and the maximum output power is -16.7 dBm. The total power consumption is 9.27 mW. The FOM is -176.3 dBc/Hz. Chapter 3 presents two V-band VCO topologies. The first circuit was fabricated in UMCTM 90 nm CMOS. This topology provides a self-detected circuit to reduce the threshold voltage. Therefore, this VCO can reduce the power consumption. The measured oscillation central frequency is 50.7 GHz with the tunable frequency range from 50.25 to 51.5 GHz. The phase noise is -123.9 dBc/Hz at 10 MHz offset, and maximum output power is -8.34 dBm. The total power consumption is 25.44 mW. The FOM is -183.9 dBc/Hz. The second circuit was fabricated in tsmcTM 90 nm CMOS. This topology is darlinton pair, and using transformer feedback. Therefore, the source voltage become active. The transistor can work in saturation. The measured oscillation central frequency is 54.23 GHz with tunable frequency range from 53.82 to 55.62 GHz. The phase noise is -113.09 dBc/HZ at 10 MHz offset, and the maximum output power is -6.14 dBm. The total power consumption is 11.3 mW. The FOM is -177.2 dBc/Hz. Chapter 4 develops a V-band third sub-harmonic injection lock oscillator topology which was fabricated in UMCTM 90 nm CMOS technology. This third sub-harmonic injection lock oscillator used two feedback paths to increase the third-harmonic power. Therefore, it can increase the locking range. The measured free run frequency of oscillator is 41.45 GHz. The locking range is from 39.32 to 41.91 GHz. The power consumption is 19.18mW. The phase noise is -114.1 dBc/Hz at 1 MHz offset which VCO is under injection locked. The maximum output power is -4.17 dBm. The FOM is 0.33. Finally, the conclusion and future work are given in Chapter 5.