The Study on fT-Doubler and Passive Combiner Techniques for Low Power Millimeter-Wave Mixer Designs

• Main Authors: Jia-Ren Liang, 梁嘉仁
• Other Authors: Hwann-Kaeo Chiou
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/50036950894249371106

碩士 === 國立中央大學 === 電機工程研究所 === 99 === This thesis develops millimeter mixer circuits. Two kinds of mixers are studied. First, a 60 GHz low power double-balanced gate-pumped (DGP) mixer with passive combiner techniques is designed in tsmcTM CMOS 90 nm process. Using the power combiner and body coupling techniques, the proposed DGP mixer achieves a conversion gain of 3.4 dB, an input 1-dB compression point of - 5 dBm, an input IP3 of 6 dBm at 1-dBm LO power. The LO-RF and LO-IF, and RF-IF isolations are better than 33 dB, 33 dB and 27 dB. The core power consumption is only 0.9 mW and the chip size occupies 0.63 mm2. Second. a fT-doubler topology is adopted to three mm-wave mixer designs. The fT-doubler topology is also called as Darlington pair which improves the fT frequency. Compared with a single CMOS transistor, the fT frequency can arise approximately twice times. Thus, the topology also increases the operating frequency and provides sufficient current gain in millimeter frequencies. The first fT-doubler mixer is a 28 GHz low power high gain double-balanced mixer fabricated in tsmcTM CMOS 0.18 um process. To use the PMOS transistor for the mixer circuit design can reduce the overdrive voltage of the LO switches and the total power consumption. The proposed mixer achieves a conversion gain of 8.1 dB, an input 1-dB compression point of - 6 dBm, an input IP3 of 7 dBm at – 1-dBm LO power. The LO-RF, LO-IF, and RF-IF isolations are better than 23 dB, 44 dB and 33 dB. The core power consumption is only 4.95 mW and the chip size occupies 0.7 mm2. The second fT-doubler mixer is a 60 GHz double-balanced mixer with lumped Wilkinson power combiner fabricated in WINTM pHEMT 0.15 um process. The passive combiner is realized by lumped Wilkinson power combiner which combines the RF with LO signals. Compared with the conventional Wilkinson power combiner, the proposed structure has significant size reduction. Besides, the combined signals are injection into each gate terminal of two coupled fT-doubler topologies to yield the frequency conversion. The fT-doubler topology acts as the transconductance stage of the mixer which not only increases the conversion gain but also improves the port-to-port isolations. The proposed mixer shows a conversion gain of 2.2 dB, an input 1-dB compression point of - 6 dBm, an input IP3 of 4 dBm at 1-dBm LO power. The LO-RF, LO-IF, and RF-IF isolations are better than 13 dB, 32 dB and 44 dB. The core power consumption is 155 mW and the chip size occupies 1.5 mm2. Finally, the third fT-doubler mixer is a 50 GHz low power double-balanced gate-pumped mixer with passive combiner techniques fabricated in UMCTM CMOS 90 nm process. The circuit topology is same as the first one. The input RF and LO signals can be combined by using the passive combiner techniques. Then, the combined signals are injection into each gate terminal of two coupled fT-doubler of the double-balanced mixer to perform the frequency conversion. The proposed mixer obtains a conversion gain of 0 dB, an input 1-dB compression point of - 6 dBm, an input IP3 of 4.3 dBm at 0-dBm LO power. The LO-RF, LO-IF, and RF-IF isolations are better than 29 dB, 35 dB and 27 dB. The core power consumption is only 2.8 mW and the chip size occupies 0.54 mm2.