Design of Antenna-Configurable MIMO Detector with High Speed Sorting Architectures

碩士 === 國立中央大學 === 電機工程研究所 === 99 === In this thesis, we proposed a MIMO detector which can support multiple antenna types (6×6, 5×5, 4×4, 3×3, and 2×2), various modulation schemes (64-QAM, 16-QAM, QPSK, and BPSK) and K-value (K=10). From the algorithm aspects, we deigned a modified K-best algorithm...

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Main Authors: Hsuan-Kuei Huang, 黃宣貴
Other Authors: Muh-Tian Shiue
Format: Others
Language:zh-TW
Published: 2011
Online Access:http://ndltd.ncl.edu.tw/handle/79172540868169220519
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spelling ndltd-TW-099NCU054420642017-07-15T04:29:01Z http://ndltd.ncl.edu.tw/handle/79172540868169220519 Design of Antenna-Configurable MIMO Detector with High Speed Sorting Architectures 含高速化排序架構之天線組態可變的多輸入輸出解碼器設計 Hsuan-Kuei Huang 黃宣貴 碩士 國立中央大學 電機工程研究所 99 In this thesis, we proposed a MIMO detector which can support multiple antenna types (6×6, 5×5, 4×4, 3×3, and 2×2), various modulation schemes (64-QAM, 16-QAM, QPSK, and BPSK) and K-value (K=10). From the algorithm aspects, we deigned a modified K-best algorithm (MKB) can reduce the number of sorting layer from 2Nt to Nt, compared with the conventional K-best algorithm. The MKB also include the Code-Book Enumeration to reduce number of visted nodes from K×√(M ) to K×e.To further enhance sorting performance, we design the Paralled-Slice Merge algorithm(PSMA) and Parallel Bubble-Slice sort(PBSS). In terms of hardware implementation, the MKB and sorting circuit are designed as elementary building blocks. With these building blocks, the proposed MIMO detector can flexibly achieve the configurable architecture. In order to simplify the multiplier complexity, we propose a novel shift-multiplier (SM) to replace the conventional multiplier. Finally, the proposed configurable MIMO detector is verified by the SIMIS VeriEnterprise Xilinx FPGA development board. Muh-Tian Shiue 薛木添 2011 學位論文 ; thesis 106 zh-TW
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description 碩士 === 國立中央大學 === 電機工程研究所 === 99 === In this thesis, we proposed a MIMO detector which can support multiple antenna types (6×6, 5×5, 4×4, 3×3, and 2×2), various modulation schemes (64-QAM, 16-QAM, QPSK, and BPSK) and K-value (K=10). From the algorithm aspects, we deigned a modified K-best algorithm (MKB) can reduce the number of sorting layer from 2Nt to Nt, compared with the conventional K-best algorithm. The MKB also include the Code-Book Enumeration to reduce number of visted nodes from K×√(M ) to K×e.To further enhance sorting performance, we design the Paralled-Slice Merge algorithm(PSMA) and Parallel Bubble-Slice sort(PBSS). In terms of hardware implementation, the MKB and sorting circuit are designed as elementary building blocks. With these building blocks, the proposed MIMO detector can flexibly achieve the configurable architecture. In order to simplify the multiplier complexity, we propose a novel shift-multiplier (SM) to replace the conventional multiplier. Finally, the proposed configurable MIMO detector is verified by the SIMIS VeriEnterprise Xilinx FPGA development board.
author2 Muh-Tian Shiue
author_facet Muh-Tian Shiue
Hsuan-Kuei Huang
黃宣貴
author Hsuan-Kuei Huang
黃宣貴
spellingShingle Hsuan-Kuei Huang
黃宣貴
Design of Antenna-Configurable MIMO Detector with High Speed Sorting Architectures
author_sort Hsuan-Kuei Huang
title Design of Antenna-Configurable MIMO Detector with High Speed Sorting Architectures
title_short Design of Antenna-Configurable MIMO Detector with High Speed Sorting Architectures
title_full Design of Antenna-Configurable MIMO Detector with High Speed Sorting Architectures
title_fullStr Design of Antenna-Configurable MIMO Detector with High Speed Sorting Architectures
title_full_unstemmed Design of Antenna-Configurable MIMO Detector with High Speed Sorting Architectures
title_sort design of antenna-configurable mimo detector with high speed sorting architectures
publishDate 2011
url http://ndltd.ncl.edu.tw/handle/79172540868169220519
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