A Wide Range Delay-Locked Loop with Phase Error Calibration and Frequency Multiplier
碩士 === 國立中央大學 === 電機工程研究所 === 99 === This study presents a wide-range and multiphase DLL-based clock generator with the Phase Error Compensation loop. For more applications, we proposed a frequency multiplier to synthesize a combined clock. In this voltage control delay line, we take the multi-gai...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94233088302678434259 |