| Summary: | 碩士 === 國立交通大學 === 電機學院通訊與網路科技產業專班 === 99 === ABSTRACT
As the rapid development of the Internet, the requirement of synchronization between distributed devices increases. This thesis addresses this issue with high-precision time synchronization protocol (Precision Time Protocol, PTP which is also called IEEE 1588), the hierarchical master-slave structure and time stamp transceiver technology as the system model.
Since the current Internet uses the packet-switching technology, there could be a large packet delay variation (PDV) at the receiver. Moreover, the receiver clock is likely to have frequency skew and time offset with respect to the transmitter clock.
In this thesis, we design and implement an effective clock synchronization algorithm. Under heavy traffic load and large packet delay variation situations, our proposed algorithm can provide good estimates of frequency skew and time offset. The precision achieved by our proposed algorithm is sub-microsecond (<10-6 sec).
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