| Summary: | 碩士 === 國立交通大學 === 電控工程研究所 === 99 === A broadcast interconnects method for 3D-IC applications is implemented by using common conduction layer. Die-to-Die Multi-signaling communication mechanism with common conduction layer has shorter communication distance. Compared with wireless or wire interconnect. Our communication distance is 2um. The shorter distance means that it can resist the neighborhood noise and increase the IO density for packaging. Moreover, chip thinning, together with device scaling, will further improve the density and performance of the vertical I/Os. As a result, because of the larger I/O count possible in 3D integration and the short length of the interconnections, it is expected that the vertical I/Os between stacked chips will be able to provide the high data bandwidth required by Moore’s law with the benefit of low-power signaling.
We also use alignment method for detecting position error. In our design, a buffer stage may be needed between the circuit blocks in different layers, since common conduction layer usually have a much larger Parasitic Resistance than interconnects of circuits. This interconnect has energy efficiency of 0.18 pJ/bit at 2Gbps. The proposed broadcast interconnects method is implemented in TSMC 0.18um process for demonstration of this architecture.
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