| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 99 === In this thesis we design an all-digital phase-locked loop (PLL) with ultra-wide capture range which spans from 1kHz to 1MHz. The ratio of the highest frequency to the lowest frequency is 1000 and there is no need for prior information of the input frequency. With this PLL, all applications whose working frequency is within this frequency range could use it to implement the corresponding system. Also, for applying it in noisy environment, the PLL is asked to have good noise immunity. It is designed to work efficiently when SNR=0dB. On designing this PLL, we focus on three aspects: the frequency locked rate, the lock efficiency and the capability of anti-frequency drift. For good efficiency in every aspect within wide capture range under noisy environment, we design three different states which include the acquisition state, the tracking state and the phase-fixing state. Moreover, we introduce the dual-loop system to further improve the performance. Finally, to verify the feasibility of our approach, we implement this PLL by Hardware Description Language based on all-digital design.
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