Compact Physical-Based Model and Applications of Dynamic-Threshold-Metal-Oxide-Semiconductor

• Main Authors: Wang, Kuan-Ti, 王冠迪
• Other Authors: Chao, Tien-Sheng
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/95516093170029989045

博士 === 國立交通大學 === 電子物理系所 === 99 === First, we use the maximum transconductance linear extrapolated method to extract VTH of DTMOS. It can largely reduce drafting time of extracting VTH of DTMOS by using this method. Furthermore, we lead the equivalent potential concept into DTMOS to indicate the channel potential control ability of both gate and source terminals with using band diagram, simultaneously. It deduces the m-model for extracting body effect coefficient without complicated variable substrate bias and fitting process. In addition, the penetration electric field from drain/source can be suppressed by the forward body bias of DTMOS, especially for short channel device. As a result, it improves the short channel effect (~9%) in DT technology due to decreasing of charge sharing effect. Then, we use split C-V to extract the effective mobility of DTMOS. Comparing to normal device, the higher mobility (~32%) of DTMOS can be attributed to the decreasing of normal electrical field for minor depletion region. The effect oxide thickness about 4 A of DTMOS can be reduced by using metal gate (TiN、TaC) to replace poly gate. It achieves by eliminating poly gate depletion. Besides, we prove that DTMOS owns the lower ballistic transport coefficient with higher injection velocity from source terminal due to its suppression of DIBL effect. For the first time, high-performance with superior reliability characteristics is demonstrated in a NOR-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory device, with multilevel and 2-bit/cell operation. The DTSSI programming mechanism was thoroughly investigated using the Integrated Systems Engineering (ISE) TCAD simulation tools combining the fabrication procedure and physical models. Results show the major factors affecting the DTSSI technique, including the supply current, and the lateral and vertical electric fields between the neutral-gap regions in the WSG-SONOS memory cell. Moreover, a programming mechanism for conventional source-side injection (Normal-mode), substrate-bias enhanced source-side injection (Body mode) and dynamic-threshold source-side injection (DT mode) of wrapped-select-gate SONOS (WSG-SONOS) memory is also developed with 2-D Possion equation and hot-electron simulation and programming characteristics measurement for NOR flash memory. Compared with traditional SSI, the DTSSI mechanisms are enhanced in terms of lateral acceleration electric field (~6%) and supply current (~450%) in the neutral gap region, resulting in high programming efficiency. It also provides lower power consumptions (~25% decrease). Finally, the high-performance (?谽GM=200ns/?覟RS=5ms) with low supply current in DT mode is used to achieve the multilevel and 2-bit/cell operation. Using the DTSSI enables easy extraction of the multilevel states with tight VTH distribution, nearly negligible second-bit effect, superior endurance characteristics, and good data retention. Finally, we discuss DTMOS with regard to operation temperature effect. We find a zero-temperature-coefficient point with no current variation at elevated temperature in DT mode operation. The main reason is that compensation between threshold voltage and mobility at elevated temperature. Once operating the device with higher gate voltage than ZTC point, the phonon effect would degrade on current of device. On the contrary, the lower operation gate voltage than ZTC point would enhance the driving current due to its low threshold voltage at higher operation temperature. The decrease of threshold voltage is result from the increase of intrinsic density of material at elevated temperature. As a result, predicting the location of ZTC point precisely is very important to design device at different operation temperature. It can help to perform the circuit more stable and work well. Here, we propose a clear and simple ZTC point modeling of DTMOS with considering physical insights carefully. Using our DTMOS ZTC modeling, the mismatch value between our model and experimental data, no matter long channel or short channel device, can be reduced lower than 2%. Furthermore, the ZTC point of DTMOS can also be consistent by extracting from fixed body bias experimental data. It shows that optimum ZTC point of device can be adjusted by the body effect coefficient, work function and alpha ratio. Consequently, our model provides a design guideline for green DT technology.