Fast Analog Layout Prototyping for Nanometer Design Migration

• Main Author: 翁逸芃
• Other Authors: 陳宏明
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/06083367953705453093

碩士 === 國立交通大學 === 電子研究所 === 99 === Traditional migration technology often generates a single layout that has exactly the same topology with the original one. However, as a circuit is retargeted to a new technology or new specification, the new result with exactly the same topology may not be the desired placement in the migrated technology because of the layout dimension or the layout area. In order to provide sufficient flexibility for designers, a new migration algorithm proposed in this thesis is able to quickly provide multiple results while keeping similar circuit performance. First, various placement constraints, including topology, matching, and symmetry, are extracted from the original layout. The extracted constraints are hierarchically stored into a topology slicing tree. Based on this tree, placement is performed from the bottom tree nodes to the root tree node to record multiple placements for the subtree. As a result, all possible placements under the constraints will be fully explored. The experimental results validate that our approach can provide reasonable layouts, even a better result almost in no time.