Area-Efficient Soft BCH and RS Decoders

• Main Authors: Lin, Yi-Min, 林義閔
• Other Authors: Lee, Chen-Yi
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/60138007933203236495

博士 === 國立交通大學 === 電子研究所 === 99 === This dissertation investigates the soft BCH and RS decoders from algorithms to architecture designs and circuit implementation. Two different decoding schemes are studied, including the error magnitude (EM) type and Chase-type soft decoding algorithms. For higher error correcting performance with the same code rate, soft decoding algorithms of error control codes are the most popular methods and have aroused many research interests in BCH and RS decoding. As compared with traditional hard decoders, soft decoders provide better error correcting performance but much higher hardware complexity. In this dissertation, the EM-type soft decoding algorithms are firstly proposed for BCH codes to provide low hardware complexity by dealing with the least reliable bits. The low complexity EM-type approach can provide lower hardware complexity than the hard decoder but has to exploit higher reliable soft information for maintaining the error correcting performance. On the other hand, the high performance EM-type approach has similar concept as low complexity EM-type approach but compensates one extra error outside the least reliable set, leading to better performance while providing comparable hardware complexity. The Chase-type soft decoding algorithms are discussed for providing more general low complexity decoding methods for both BCH and RS codes. Instead of utilizing various hard decoders to decode all candidate sequences simultaneously, a decision-eased soft decodingscheme is provided to process Chase algorithm with one hard decoder module. In addition, a simplified decision making unit is proposed to determine the most likely codeword with Hamming distance calculations. Moreover, the decision making unit can be eliminated with the proposed decision-confined soft decoding algorithm. By confining the degree of error location polynomial generated from the key equation solver, our proposal only needs to completely decode one candidate sequence. Four implemented works are presented in this dissertation. A 26.9 K 314.5 Mb/s soft (32400, 32208; 12) BCH decoder chip is designed for DVB-S2 system based on low complexity EM-type approach. The proposed soft BCH decoder can achieve 314.5 Mb/s with 50.0% gate-count reduction in contrast to a 99.3 Mb/s traditional hard BCH decoder in CMOS 90 nm technology. The second designs are high performance EM-type soft BCH (255, 239; 2) and (255, 231; 3) decoders. Our proposed soft BCH decoders can achieve at most 0.75 dB coding gain at 10^-5 BER with one extra error compensation and 5% less area than traditional hard BCH decoders. The third design is a 30 K 2.5 Gb/s decision-eased soft RS (224, 216; 4) decoder for millimeter-wave (mmWave) system, which has 0.5 dB coding gain at 10^-5 BER as compared with the conventional hard decoder. The remaining design is a decision-confined soft RS (255, 239; 8) decoder chip for optical communications, which can provide 0.4 dB coding gain at 10^-4 CER over hard decoders and achieve 2.56 Gb/s throughput with gate count of 45.3 K. All the implementation results reveal the positive consequence as expected.