Design of STBC OFDM Interference Canceller for High-Mobility Wireless Metropolitan Area Network

碩士 === 國立交通大學 === 電子研究所 === 99 === In recent years, space time block code (STBC) has been shown to give high code rate and good performance. It is suggested to be applied in an orthogonal frequency division multiplex (OFDM) system since OFDM system with multiple antennas can provide better communica...

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Bibliographic Details
Main Authors: Chang, Wei-Kai, 張為凱
Other Authors: Jou, Shye-Jye
Format: Others
Language:zh-TW
Published: 2010
Online Access:http://ndltd.ncl.edu.tw/handle/75855940036793564969
Description
Summary:碩士 === 國立交通大學 === 電子研究所 === 99 === In recent years, space time block code (STBC) has been shown to give high code rate and good performance. It is suggested to be applied in an orthogonal frequency division multiplex (OFDM) system since OFDM system with multiple antennas can provide better communication performance by exploiting transmit diversity and it was also supported by IEEE 802.16e/m standard. Nevertheless, STBC is sensitive to the temporal channel variation inside one code word which results in the symbols inside one codeword interferes with each other. Also, time-varying multipath channel introduces intercarrier interference (ICI) among OFDM subcarriers. These interference noises degrade STBC-OFDM system performance. Hence, an STBC interference cancellation scheme is required for better performance when the detailed channel statistics information (CSI) variation is unavailable. This thesis proposes an STBC interference canceller for any STBC-OFDM systems with two transmit antenna and one receive antenna in mobile environment. The proposed STBC interference canceller is applied in an existed IEEE802.16e STBC-OFDM receiver and can easily be adapted into IEEE802.16m STBC-OFDM receiver, too. The proposed design aims to provide performance improvement under the vehicle speed up to 360 km/hr. The performances have been demonstrated through the simulation of the proposed design with a previously proposed two-stage channel estimator. At vehicle speed of 240 and 360 km/hr and signal to noise ratio (SNR) over 15dB for 16 quadrature amplitude modulation (16QAM), the proposed design can provide more than 2 times bit error rate (BER) improvement. The proposed design is implemented in 90 nm CMOS technology. The gate count is 42,277 and the power dissipation is 1.45 mW at 78.4 MHz operation frequency from a supply voltage 1V. About 61% gates of our proposed STBC interference canceller are shared with the existed two-stage channel estimator design, and the overhead is only 4.9%.