Generic Integer Linear Programming Formulation for 3D IC Partitioning
碩士 === 國立交通大學 === 電子研究所 === 99 === As technology advances, 3D IC has gradually become a trend, because it is a novel technology, it requires new EDA technology, and partitioning is one of important items. This paper focus on partitioning from the architectural level, in order to maximize its benef...
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ndltd-TW-099NCTU54281092015-10-13T20:37:08Z http://ndltd.ncl.edu.tw/handle/30985216131621011683 Generic Integer Linear Programming Formulation for 3D IC Partitioning 適用於三維積體電路之線性規劃 Mei, Tsung-Wan 梅宗菀 碩士 國立交通大學 電子研究所 99 As technology advances, 3D IC has gradually become a trend, because it is a novel technology, it requires new EDA technology, and partitioning is one of important items. This paper focus on partitioning from the architectural level, in order to maximize its benefit. First, we use the logical operators to solve the problem of 3D IC partitioning, and converted into integer linear programs (ILPs). Our ILP formulation can reduce the number of TSV and power, and because of its flexibility, it can be expanded to support multiple supply voltage designs. We propose two methods to speed up the ILP computation, Experimental results show that our method can effectively reduce the ILP computation time. In addition, our method also has great flexibility in space, by restrictions on changes or new ILP formula can easily be extended to different target partitioning problem. This flexibility makes the ILP formula we can easily solve the general 3D IC partitioning problem. Jiang, Iris Hui-Ru 江蕙如 2010 學位論文 ; thesis 33 zh-TW |
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碩士 === 國立交通大學 === 電子研究所 === 99 === As
technology advances, 3D IC has gradually become a trend, because it is a
novel technology, it requires new EDA technology, and partitioning is
one of important items. This paper focus on partitioning from the
architectural level, in order to maximize its benefit. First, we use the
logical operators to solve the problem of 3D IC partitioning, and
converted into integer linear programs (ILPs). Our ILP formulation can
reduce the number of TSV and power, and because of its flexibility, it
can be expanded to support multiple supply voltage designs. We propose
two methods to speed up the ILP computation, Experimental results show
that our method can effectively reduce the ILP computation time. In
addition, our method also has great flexibility in space, by
restrictions on changes or new ILP formula can easily be extended to
different target partitioning problem. This flexibility makes the ILP
formula we can easily solve the general 3D IC partitioning problem.
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author2 |
Jiang, Iris Hui-Ru |
author_facet |
Jiang, Iris Hui-Ru Mei, Tsung-Wan 梅宗菀 |
author |
Mei, Tsung-Wan 梅宗菀 |
spellingShingle |
Mei, Tsung-Wan 梅宗菀 Generic Integer Linear Programming Formulation for 3D IC Partitioning |
author_sort |
Mei, Tsung-Wan |
title |
Generic Integer Linear Programming Formulation for 3D IC Partitioning |
title_short |
Generic Integer Linear Programming Formulation for 3D IC Partitioning |
title_full |
Generic Integer Linear Programming Formulation for 3D IC Partitioning |
title_fullStr |
Generic Integer Linear Programming Formulation for 3D IC Partitioning |
title_full_unstemmed |
Generic Integer Linear Programming Formulation for 3D IC Partitioning |
title_sort |
generic integer linear programming formulation for 3d ic partitioning |
publishDate |
2010 |
url |
http://ndltd.ncl.edu.tw/handle/30985216131621011683 |
work_keys_str_mv |
AT meitsungwan genericintegerlinearprogrammingformulationfor3dicpartitioning AT méizōngwǎn genericintegerlinearprogrammingformulationfor3dicpartitioning AT meitsungwan shìyòngyúsānwéijītǐdiànlùzhīxiànxìngguīhuà AT méizōngwǎn shìyòngyúsānwéijītǐdiànlùzhīxiànxìngguīhuà |
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1718048949388967936 |