| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 99 === As
technology advances, 3D IC has gradually become a trend, because it is a
novel technology, it requires new EDA technology, and partitioning is
one of important items. This paper focus on partitioning from the
architectural level, in order to maximize its benefit. First, we use the
logical operators to solve the problem of 3D IC partitioning, and
converted into integer linear programs (ILPs). Our ILP formulation can
reduce the number of TSV and power, and because of its flexibility, it
can be expanded to support multiple supply voltage designs. We propose
two methods to speed up the ILP computation, Experimental results show
that our method can effectively reduce the ILP computation time. In
addition, our method also has great flexibility in space, by
restrictions on changes or new ILP formula can easily be extended to
different target partitioning problem. This flexibility makes the ILP
formula we can easily solve the general 3D IC partitioning problem.
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