| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 99 === With fastest access speed among semiconductor memories, embedded Static Random Access Memory (SRAM) plays an important role in various System-on-Chip (SoC) designs. Due to its large ratio, low voltage operation capability of SRAM can lower the total system power significantly. But technology scaling, variation severely degrades functionality of digital circuit. In this thesis, a Data-Aware dynamic supply Write-Assist scheme is proposed and implemented with 128Kb cross-point 8T SRAM. This technique improves Write margin over 20% on average at operating voltage ranges from 0.5V to 0.8V, and features good anti-variation ability with minimum area overhead. Meanwhile, Write performance improves to pico-second scale, otherwise would fail if no Write assist technique is applied, on average at operating voltage ranges from 0.5V to 0.8V. Simulation results show that chip operation speed achieves 474MHz at VDD = 0.6V.
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