Design of Ultra-Low-Power Disturb-Free Cross-Point 8T SRAMs

• Main Authors: Hsia, Mao-Chih, 夏茂墀
• Other Authors: Chuang, Ching-Te
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/38179308560211371035

碩士 === 國立交通大學 === 電子研究所 === 99 === Low power design in Static Random Access Memory (SRAM) has become one of the mainstreams as a respond to the increasing usage of handheld device in that portable device requires a less power consumption chip to extend its working time. Nearly 90% area of a chip will be occupied by embedded SRAM in 10 years to come in accordance with ITRS2005 predictions which means that diminish power on SRAM will directly lead to chip power reduction. This thesis presents a power control technique to minimize the array power consumption of single-ended Read/Write 8T SRAM. By obtaining current balance between keepers of virtual cell supply and cell leakage, it allows a fall of virtual cell supply which is power supply of cell array. That leads to reduction of array power and improvement on write ability. Half Select Noise Margin (HSNM) is guaranteed safe by constructing an algorithm to size virtual cell supply keepers. To further improve read power, another structure is proposed to charge the virtual cell supply of selected column solely instead of all columns of selected rows. Both ALP and ULP SRAM achieves the power saving purpose compared to novel 8T SRAM and its VCCMIN is 0.45V.