| Summary: | 博士 === 國立交通大學 === 電子研究所 === 99 === In a modern communication receiver, the received continuous-time analog signal is quantized into a discrete-time digital sequence by an analog-to-digital converter (ADC)
so that the complex signal processing can be performed in the digital domain. The ADC requires a periodic clock as a timing reference for input sampling. If the sampling clock
exhibits jitter, the ADC suers from sampling errors and its signal-to-noise ratio (SNR) performance is degraded. For a low-speed low-resolution ADC, the sampling error due to clock jitter is not crucial. As the progress of advanced communication system, the operation speed and the resolution of the ADC are also increased. An accurate sampling clock is essential for a high-speed high-resolution ADC.
Clock jitter can be measured and digitized by a time-to-digital converter (TDC). With appropriate calibration technique, the output code of the TDC can be translated in to the corresponding jitter information. This jitter information is then used to compensate the ADC D s sampling error in the digital domain, improving the ADC D s SNR performance.
This thesis presents a clock jitter measurement and compensation scheme for analog-to-digital converters.
A 7-bit 80-MS/s TDC was fabricated using a 65 nm CMOS technology. The clock jitter of an ADC is measured by the TDC. We also demonstrate a new digital calibration
technique for the TDC. The calibration can be performed in the background without interrupting the normal ADC and TDC operation. The proposed technique is immune to device and interconnection mismatches, and is not sensitive to the waveforms of the input
clocks either. The resolution of the 7-bit TDC is 0.27 ps. The TDC occupies a die area of 0.1mm^2 while consuming 20 mW from a 1.2 V supply. The TDC is applied to a 16-bit ADC for the clock jitter measurement and compensation. Two dierent system scenarios are covered: 1) an ADC with a clean external clock and 2) an ADC with an external clock as the main jitter source. For the first scenario,
the SNR of the 16-bit ADC is improved from 71.2 dB to 77.3 dB for an optimized delay-locked loop (DLL) and 60.8 dB to 74.4 dB for an ill-conditioned DLL by the jitter correction at a sine wave input frequency of 29 MHz. For the second scenario, the proposed jitter correction technique achieves an equivalent sampling jitter root-mean-squared value (rms) of 4 ps when the jitter rms of the original sampling clock is 8.2 ps.
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