| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 99 === This thesis provides an architectural design filter in AVC/H.264 video codec, which supports the picture-adaptive field/frame mode and the macroblock-adaptive field/frame mode. Using a top-down design methodology, complexity analysis on the de-blocking filter algorithm was done to find a relation between the parallelism of the processing element (PE) of the de-blocking filter and the system operation frequency in a critical condition. Design space exploration was performed on different data granularities to determine a relation between the peak bandwidth and memory requirement. The parallelism of the PE can be determined based on the system operation frequency for maintaining the usage efficiency of the PE. A proper data granularity can be selected to serve as a data unit for processing, by striking a compromise between peak bandwidth and memory requirement.
In addition, based on data dependency of the de-blocking filter algorithm, data flow corresponding to different processing orders of edge in a block corresponding to the determined data granularity was explored. From the data flow, the corresponding hardware requirements could be determined. Hence, with consideration of the system operation frequency, the corresponding hardware requirement, and data reuse, the proper processing order of edge is further determined, and the de-blocking filter architecture design is developed to conform to an application requirement. The architectural design of the de-blocking filter is developed based a decoder system. Interfaces and data communication between the de-blocking filter architecture and each related module were also taken into consideration.
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