The Low Noise Amplifier Design for WLAN 802.11a/b/g and 60GHz Applications

• Main Authors: Chi-Chen Chang, 張綺真
• Other Authors: 江衍忠
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/84261824563313290286

碩士 === 國立中興大學 === 電機工程學系所 === 99 === This thesis focuses on the low noise amplifier design of RF receivers for WLAN 802.11a/b/g dual-band and 60GHz applications, in which we cover the topics including introduction to bands and applications, literature review, circuit designs, chips’ measurement results and discussions of the results. There are four chapters to discourse on the basis of low noise amplifier design, and circuit implementations. In Chapter 1, we introduce the wireless RF system, IEEE 802.11 bands, and optical transmission and wireless communications systems development. In Chapter 2, important parameters of LNA are described, including introduction, impedance matching theory, matching network design, noise figure, linearity, and stability. Chapter 3 is focused on the design of a sub 1V CMOS low noise amplifier for dual-band application. This chapter starts from studying three basic topologies for LNA, including their matching design and noise ability. Then we use low voltage characteristics of the folded cascode circuit to design a low power consumption circuit for 2.4GHz/5GHz dual band application. The chip is implemented using TSMC 0.18um CMOS process technology. The measured peak gains are 13.9 dB and 9.6dB at frequencies 2.4GHz and 5GHz, respectively. The measured noise figures are 3.9 dB and 4.7 dB, respectively, for both bands. The power consumption of the circuit is 5.5mW under 1V supply voltage. The subject of Chapter 4 is the 60GHz low noise amplifier design using GaAs process technology, and probing the technology behavior of the GaAs process and its applications. This chip is fabricated using WIN 0.15um pHEMT process. The measured peak gain of this 60GHz GaAs LNA is 11dB at 55.7GHz, and the measured noise figure is 4.8dB. The power consumption of the circuit is 26.6mW under 1.8V supply voltage. In Chapter 5, a 60GHz LNA using TSMC 90nm CMOS process technology is presented. The measurement results show a 6.57 dB gain and a 7.4 dB noise figure at 59GHz. The power consumption of the circuit is 9.4mW under 1.2V supply voltage.