Clock Tree Optimization with Prebond Testability in 3D IC

碩士 === 中興大學 === 資訊科學與工程學系所 === 99 ===

Bibliographic Details
Main Authors:	Yu-Chang Hung, 洪毓章
Other Authors:	王行健
Format:	Others
Language:	zh-TW
Published:	2011
Online Access:	http://ndltd.ncl.edu.tw/handle/40070693331296618063

id	ndltd-TW-099NCHU5394074
record_format	oai_dc
spelling	ndltd-TW-099NCHU53940742015-10-13T20:18:51Z http://ndltd.ncl.edu.tw/handle/40070693331296618063 Clock Tree Optimization with Prebond Testability in 3D IC 針對三維晶片之未接合可測試性時脈樹最佳化 Yu-Chang Hung 洪毓章碩士中興大學資訊科學與工程學系所 99 王行健 2011 學位論文 ; thesis 44 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 中興大學 === 資訊科學與工程學系所 === 99 ===
author2	王行健
author_facet	王行健 Yu-Chang Hung 洪毓章
author	Yu-Chang Hung 洪毓章
spellingShingle	Yu-Chang Hung 洪毓章 Clock Tree Optimization with Prebond Testability in 3D IC
author_sort	Yu-Chang Hung
title	Clock Tree Optimization with Prebond Testability in 3D IC
title_short	Clock Tree Optimization with Prebond Testability in 3D IC
title_full	Clock Tree Optimization with Prebond Testability in 3D IC
title_fullStr	Clock Tree Optimization with Prebond Testability in 3D IC
title_full_unstemmed	Clock Tree Optimization with Prebond Testability in 3D IC
title_sort	clock tree optimization with prebond testability in 3d ic
publishDate	2011
url	http://ndltd.ncl.edu.tw/handle/40070693331296618063
work_keys_str_mv	AT yuchanghung clocktreeoptimizationwithprebondtestabilityin3dic AT hóngyùzhāng clocktreeoptimizationwithprebondtestabilityin3dic AT yuchanghung zhēnduìsānwéijīngpiànzhīwèijiēhékěcèshìxìngshímàishùzuìjiāhuà AT hóngyùzhāng zhēnduìsānwéijīngpiànzhīwèijiēhékěcèshìxìngshímàishùzuìjiāhuà
_version_	1718045954345533440

Clock Tree Optimization with Prebond Testability in 3D IC

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