| Summary: | 碩士 === 國立高雄應用科技大學 === 光電與通訊研究所 === 99 === Today, there is no doubt that the screen printing is a viable method for chip producing of surface mount devices. However, reality dictates that much careful planning and control over many variables is necessary in order to create the required efficient printing system. Material type, paste consistency, desired throughput, feed rates, film thickness, and print head design, are but a partial list of the variable components affecting the printing operation. Also, because of the mechanical constraints induced by printing, resistor films tend to break easily thus rendering the pieces unusable. This means a large amount of scrap chips are required for qualifications.
In this thesis, a screen printing inspector has been designed to suit in a production line environment, and help the producer check if the printing area is manufactured to specification. We present an efficient algorithm for printing area extraction based on the proposed SVD enhancement and Otsu binarization to robustly detect and segment the printing area. Due to the possible translation and rotation errors caused by the x-y table of the mechanism, alignment calculated by the least mean square algorithm is then carried out to prevent unsatisfactory positioning from reaching the printing area inspection. Finally, marks on resistors with resistance over specification are recorded for statistical analysis of production. Our method does not need pre-training, but running faster, and provides a better way with more effective, higher flexibility, and immediate feedback to the printing operation. An experiment using real data collected from a factory at Kaohsiung is conducted to validate the performance of the proposed framework. The accurate acceptance rate and the accurate rejection rate are 97.38 and 98.87%, respectively, while the false acceptance rate and the false rejection rate are 1.13% and 2.62%, respectively. The results demonstrate that the proposed method is sound and useful for chip resistor inspection in industry. In terms of speed, the execution time of the proposed system is directly related to the image resolution and number of resistors of the input image. For example, our system is operating at an average processing time 0.067 sec per resistor at a resolution of 320 × 240 pixels on an Intel(R) Core(TM)2 Quad Q8300 2.50GHz CPU, which makes it practical for online processing.
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