Design on SiGe Process Mixer Chip for Wireless Communication Application
碩士 === 國立金門大學 === 電資研究所 === 99 === The paper presents a novel topology of mixer. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and BJT transistor device characteristics. In the proposed topology, the LO series-parallel switch will be applied to reduce sup...
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ndltd-TW-099KMIT07060022015-10-28T04:07:06Z http://ndltd.ncl.edu.tw/handle/63319251537885166306 Design on SiGe Process Mixer Chip for Wireless Communication Application 運用於無線通訊之矽鍺(SiGe)混波器晶片設計 Wang, Song-Hao 王松豪 碩士 國立金門大學 電資研究所 99 The paper presents a novel topology of mixer. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and BJT transistor device characteristics. In the proposed topology, the LO series-parallel switch will be applied to reduce supply voltage and dc power consumption for IEEE 802.11a, IEEE 802.11b WLAN and UWB system. By using the TSMC 0.35-μm SiGe BiCMOS process technology and TSMC 0.18-μm SiGe BiCMOS process technology design, the mixer under a variety of features has a good performance. The paper proposes a mixer for IEEE802.11a WLAN application. The main advantages for mixer are low-noise, a moderate linearity, conversion gain, and isolation. The simulation results achieved are as follows: 14.1 dB power conversion gain, 0 dBm input third-order intercept point (IIP3), 6.93 dB double side band (DSB)noise figure, LO-RF, LO-IF and RF-IF isolation achieved up to 56 dB, 70 dB and 92 dB, respectively. The total dc power consumption of this mixer including output buffers is 2.31mW. The paper proposes a mixer for IEEE802.11b WLAN application. The main advantages for mixer are high-gain and, a moderate linearity, noise and isolation. The simulation results achieved are as follows: 14.99 dB power conversion gain, 0 dBm input third-order intercept point (IIP3), 7.19 dB double side band (DSB)noise figure, LO-RF, LO-IF and RF-IF isolation achieved up to 52 dB, 91 dB and 98 dB, respectively. The total dc power consumption of this mixer including output buffers is 1.94mW. The paper proposes a mixer for UWB system application. The simulation results achieved are as follows: 13.1~14.3 dB power conversion gain, -5~-4 dBm input third- order intercept point (IIP3), 10.5~ 11.5 dB double side band (DSB)noise figure, LO-RF, LO-IF and RF-IF isolation achieved up to 36~48 dB,70~99 dB and 70~79dB, respectively. The total dc power consumption of this mixer including output buffers is 3.3mW. Chen, Jun-Da 陳俊達 2011 學位論文 ; thesis 89 zh-TW |
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碩士 === 國立金門大學 === 電資研究所 === 99 === The paper presents a novel topology of mixer. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and BJT transistor device characteristics. In the proposed topology, the LO series-parallel switch will be applied to reduce supply voltage and dc power consumption for IEEE 802.11a, IEEE 802.11b WLAN and UWB system. By using the TSMC 0.35-μm SiGe BiCMOS process technology and TSMC 0.18-μm SiGe BiCMOS process technology design, the mixer under a variety of features has a good performance.
The paper proposes a mixer for IEEE802.11a WLAN application. The main advantages for mixer are low-noise, a moderate linearity, conversion gain, and isolation. The simulation results achieved are as follows: 14.1 dB power conversion gain, 0 dBm input third-order intercept point (IIP3), 6.93 dB double side band (DSB)noise figure, LO-RF, LO-IF and RF-IF isolation achieved up to 56 dB, 70 dB and 92 dB, respectively. The total dc power consumption of this mixer including output buffers is 2.31mW.
The paper proposes a mixer for IEEE802.11b WLAN application. The main advantages for mixer are high-gain and, a moderate linearity, noise and isolation. The simulation results achieved are as follows: 14.99 dB power conversion gain, 0 dBm input third-order intercept point (IIP3), 7.19 dB double side band (DSB)noise figure, LO-RF, LO-IF and RF-IF isolation achieved up to 52 dB, 91 dB and 98 dB, respectively. The total dc power consumption of this mixer including output buffers is 1.94mW.
The paper proposes a mixer for UWB system application. The simulation results achieved are as follows: 13.1~14.3 dB power conversion gain, -5~-4 dBm input third- order intercept point (IIP3), 10.5~ 11.5 dB double side band (DSB)noise figure, LO-RF, LO-IF and RF-IF isolation achieved up to 36~48 dB,70~99 dB and 70~79dB, respectively. The total dc power consumption of this mixer including output buffers is 3.3mW.
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author2 |
Chen, Jun-Da |
author_facet |
Chen, Jun-Da Wang, Song-Hao 王松豪 |
author |
Wang, Song-Hao 王松豪 |
spellingShingle |
Wang, Song-Hao 王松豪 Design on SiGe Process Mixer Chip for Wireless Communication Application |
author_sort |
Wang, Song-Hao |
title |
Design on SiGe Process Mixer Chip for Wireless Communication Application |
title_short |
Design on SiGe Process Mixer Chip for Wireless Communication Application |
title_full |
Design on SiGe Process Mixer Chip for Wireless Communication Application |
title_fullStr |
Design on SiGe Process Mixer Chip for Wireless Communication Application |
title_full_unstemmed |
Design on SiGe Process Mixer Chip for Wireless Communication Application |
title_sort |
design on sige process mixer chip for wireless communication application |
publishDate |
2011 |
url |
http://ndltd.ncl.edu.tw/handle/63319251537885166306 |
work_keys_str_mv |
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