| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 99 === In the design of three-dimensional integrated circuits (3D ICs), through-silicon-vias (TSVs) are used for data transfer across layers. However, TSVs act as obstacles during the stage of placement and routing and have a negative impact on chip yield. Therefore, TSV count minimization is an important topic for 3D IC design. In this thesis, we demonstrate that, at each control step, there often exist idle functional units and idle TSVs. If these idle functional units and idle TSVs can form alternative paths to replace direct TSVs for data transfers, the TSV count can be reduced. Based on the above observation, we propose an ILP (integer linear programming) approach to formally define and solve our problem. Given a high-level synthesis result and a clock period constraint, we use post-processing to utilize alternative paths for the minimization of TSV count. Compared with the previous work, experimental results show that our approach can further reduce TSV count without affecting the circuit performance.
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