| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 99 === In this paper, one timing-driven routing problem with consideration of interference is formulated and solved by an efficient graph-based approach. The objective of this work aims to simultaneously minimize the maximum delay from source to target, the number of via, and the potential interference nets for the multilayer routing system. To the best of our knowledge, no existing approaches in the literatures considered the interference and some papers usually improved the routing qualities by using post-processing. A space reservation technique is involved into the timing-driven router to further reduce the interference among on-chip wires and wires of boards. Second, a timing-driven partitioning, which divides the entire chip into a set of sub-regions by source position followed by the center of gravity of each sub-region, is presented to reduce the data skew. For each sub-region, the obstacle-avoiding routing algorithm is performed to connect all terminals. Experimental results show that the number of potential crosstalk nets is reduced. Moreover, the maximum delay from source to target and data skew in the routing tree are improved by 32.8% and 34 %, respectively.
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