Single-Layer RDL Routing in Flip-Chip Designs

碩士 === 中華大學 === 資訊工程學系碩士班 === 99 === Due to complication of modern IC designs, the requirement of IO count in a chip is growing continuously. Flip-chip technology has been used between IC designs and package. Because of high IO count in flip-chip technology, it makes the IOs in a complicated chip...

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Main Authors: Lu, Kai-Ping, 呂凱平
Other Authors: Yan, Jin-Tai
Format: Others
Language:zh-TW
Published: 2011
Online Access:http://ndltd.ncl.edu.tw/handle/31368557770680776974
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spelling ndltd-TW-099CHPI53920282015-10-13T20:22:59Z http://ndltd.ncl.edu.tw/handle/31368557770680776974 Single-Layer RDL Routing in Flip-Chip Designs 考量覆晶設計上單一重新分配層之繞線規劃 Lu, Kai-Ping 呂凱平 碩士 中華大學 資訊工程學系碩士班 99 Due to complication of modern IC designs, the requirement of IO count in a chip is growing continuously. Flip-chip technology has been used between IC designs and package. Because of high IO count in flip-chip technology, it makes the IOs in a complicated chip connected and the availability of IO connections improved. For RDL routing, it is lack of the results of pre-assignment in Area I/O RDL routing. In this thesis, we propose a two-phase approach to complete the RDL routing. In first phase, a given set of IO connections between IO buffers and bump balls are assigned by using routability-driven partitioning-based IO assignment. In the second phase, the RDL routing process is implemented by using the technology of net renumbering and maximal net sequence. The experimental results show that our approach can achieve 100% routability. Compared with the pre-assignment RDL router[13], our proposed approach saves 3.7% of total wirelength and 27% of CPU time for the tested examples on the average. Yan, Jin-Tai 顏金泰 2011 學位論文 ; thesis 60 zh-TW
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language zh-TW
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description 碩士 === 中華大學 === 資訊工程學系碩士班 === 99 === Due to complication of modern IC designs, the requirement of IO count in a chip is growing continuously. Flip-chip technology has been used between IC designs and package. Because of high IO count in flip-chip technology, it makes the IOs in a complicated chip connected and the availability of IO connections improved. For RDL routing, it is lack of the results of pre-assignment in Area I/O RDL routing. In this thesis, we propose a two-phase approach to complete the RDL routing. In first phase, a given set of IO connections between IO buffers and bump balls are assigned by using routability-driven partitioning-based IO assignment. In the second phase, the RDL routing process is implemented by using the technology of net renumbering and maximal net sequence. The experimental results show that our approach can achieve 100% routability. Compared with the pre-assignment RDL router[13], our proposed approach saves 3.7% of total wirelength and 27% of CPU time for the tested examples on the average.
author2 Yan, Jin-Tai
author_facet Yan, Jin-Tai
Lu, Kai-Ping
呂凱平
author Lu, Kai-Ping
呂凱平
spellingShingle Lu, Kai-Ping
呂凱平
Single-Layer RDL Routing in Flip-Chip Designs
author_sort Lu, Kai-Ping
title Single-Layer RDL Routing in Flip-Chip Designs
title_short Single-Layer RDL Routing in Flip-Chip Designs
title_full Single-Layer RDL Routing in Flip-Chip Designs
title_fullStr Single-Layer RDL Routing in Flip-Chip Designs
title_full_unstemmed Single-Layer RDL Routing in Flip-Chip Designs
title_sort single-layer rdl routing in flip-chip designs
publishDate 2011
url http://ndltd.ncl.edu.tw/handle/31368557770680776974
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