Ordered Escape Routing via Routability-Driven Pin Assignment

• Main Authors: Ke, Chung-Wei, 柯忠位
• Other Authors: Yan, Jin-Tai
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/51032343807738768422

碩士 === 中華大學 === 資訊工程學系(所) === 99 === As the feature size of microelectronic technology becomes smaller, the electronic systems become more complicated. As a result, the I/O count in a single chip has continuously been growing for complicated systems. Due to high pin counts in modern ICs, board-level routing becomes more and more difficult in board-level design. Because CAD tools fail to provide automatic routing for board-level designs, the routing for high-speed boards will become a time-consuming manual task. For board-level routing, ordered escape routing is a key problem. Hence, it is important for board-level routing to develop an efficient routing approach to complete ordered escape routing. Based on the optimality of hierarchical bubble sorting, the process of assigning routability-driven pins is firstly done for single-layer routing. Furthermore, an efficient routing approach is proposed to solve the ordered escape routing problem with the consideration of variable capacity. The experimental results show that our proposed approach achieves 100% routability for the tested examples in reasonable CPU time. Compared with the SAT-based approach for the tested examples with the capacity 1, our proposed approach reduces the CPU time by 79.5% on the average. For the tested examples with the capacity 2, our proposed approach can achieve 100% routability in reasonable CPU time.