Soft error tolerant latch design

• Main Authors: Ming Yu Lliu, 劉明諭
• Other Authors: I. C. Wey
• Format: Others
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/65134675597664163016

碩士 === 長庚大學 === 電機工程學系 === 99 === With the progress of process technology, transistor density is increased and supply voltage is scaled down, which leads to higher soft error rate. Therefore, reliability issue becomes the main design challenge in IC design. Because latch circuits are more sensitive to soft error, we proposed two kinds of soft error tolerant latches design to enhance their reliability in this thesis. The first design we proposed is an XOR gate based SEU-tolerant latch. Our design is modified from the state-of-art design, FERST. By replacing the C-element existing in the redundant path with XOR gate and added an additional feedback loop on output terminal, which can achieve higher soft error tolerance with lower short circuit power, shorter critical path delay, and lower power-delay product. The second design we proposed is an isolation type soft error tolerant latch based on preservation mechanism. Our proposed preservation mechanism includes preservation block, decision block, and feedback block. In this way, we can achieve information redundant with lower performance overhead. To avoid the internal nodes of C-element affecting by soft error, we applied preservation block and feedback block to increase the critical charge of internal nodes of C-element. In this way, we can lower the SEU rate of the whole system. As a result, we can not only achieve better soft error tolerance but also sacrifice lower power-delay product as compared with the other isolation type SEU tolerant latch designs. In tsmc 90nm process, PDP in our proposed XOR gate based SEU-tolerant latch is 1.12fJ, which improves 39.7% as compared with the FERST design. As applied the proposed XOR gate based SEU-tolerant latch to ISCAS'85 benchmark circuits, the SER improvement is 74.3% comparing with conventional latch. In tsmc 90nm process, PDP in our proposed isolation type soft error tolerant latch is 1.02fJ, which improves 45.1% as compared with the FERST design. As applied the proposed XOR gate based SEU-tolerant latch to ISCAS'85 benchmark circuits, the SER improvement is 58.3% comparing with conventional latch.