Hardware-Efficient, High-Soft-Error-Tolerant Arithmetic Circuit Design based on Most-Significant-Part Main-Block Redundancy
碩士 === 長庚大學 === 電機工程學系 === 99 === With the progress of CMOS process technology, the design complexity and the transistor density in SoC systems increase rapidly, whereas the power supply voltage also decreases rapidly. It leads to the soft-error rate in SoC designs also increasing rapidly, the relia...
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| Format: | Others |
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2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/66162346466586103868 |