Folded Photovoltaic Maximum Power Point Tracking Chip Design Based on Schedule Reordering Technique and Lookahead Restoring Divider
碩士 === 長庚大學 === 電機工程學系 === 99 === In this thesis, we proposed a new folded photovoltaic maximum power point tracking circuit based on schedule reordering technique and look-ahead restoring divider, which can effectively reduce power consumption and hardware cost. Our photovoltaic maximum power point...
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ndltd-TW-099CGU054420492015-10-13T20:27:50Z http://ndltd.ncl.edu.tw/handle/50082500358881037439 Folded Photovoltaic Maximum Power Point Tracking Chip Design Based on Schedule Reordering Technique and Lookahead Restoring Divider 以重新時序排列技術搭配前瞻判斷回存式除法器之折疊式太陽能最大功率追蹤晶片設計 Cheng Chang Chen 陳政昌 碩士 長庚大學 電機工程學系 99 In this thesis, we proposed a new folded photovoltaic maximum power point tracking circuit based on schedule reordering technique and look-ahead restoring divider, which can effectively reduce power consumption and hardware cost. Our photovoltaic maximum power point tracking algorithm is based on gain-adaptive perturb-and-observe method. It can perform with higher power conversion efficiency and response faster as weather changes and also solve the periodic disturbance problem in the traditional perturb-and-observe algorithm. With our proposed schedule reordering technique, we can solve the signal synchronization problem existing in the interface between folded maximum power point tracking circuit and photovoltaic power conversion system by adjusting folding factor and signal processing order. Through our proposed retiming and path balancing technique, we can balance the whole circuit loading to further lower power consumption in the folded maximum power point tracking circuit. With our proposed look-ahead restoring divider design, we can reduce the hardware complexity and the carry ripple switching chance in the divider. Since divider is the most complex circuit in the gain-adaptive perturb-and-observe algorithm, improvement in the divider can lower both hardware cost and power consumption in the photovoltaic power conversion system. As compared with the conventional folded photovoltaic maximum power point circuit design, we can save 40.37% transistor count and lower 78.37% power consumption while maintain the same power conversion efficiency of 97.9%. To make the whole system can be used with low-voltage solar cells, we implemented our chip in TSMC 90nmCMOS process with chip area of 1199um*679um. I. C. Wey W. Y. Lin 魏一勤 林文彥 2011 學位論文 ; thesis 71 |
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碩士 === 長庚大學 === 電機工程學系 === 99 === In this thesis, we proposed a new folded photovoltaic maximum power point tracking circuit based on schedule reordering technique and look-ahead restoring divider, which can effectively reduce power consumption and hardware cost. Our photovoltaic maximum power point tracking algorithm is based on gain-adaptive perturb-and-observe method. It can perform with higher power conversion efficiency and response faster as weather changes and also solve the periodic disturbance problem in the traditional perturb-and-observe algorithm. With our proposed schedule reordering technique, we can solve the signal synchronization problem existing in the interface between folded maximum power point tracking circuit and photovoltaic power conversion system by adjusting folding factor and signal processing order. Through our proposed retiming and path balancing technique, we can balance the whole circuit loading to further lower power consumption in the folded maximum power point tracking circuit. With our proposed look-ahead restoring divider design, we can reduce the hardware complexity and the carry ripple switching chance in the divider. Since divider is the most complex circuit in the gain-adaptive perturb-and-observe algorithm, improvement in the divider can lower both hardware cost and power consumption in the photovoltaic power conversion system. As compared with the conventional folded photovoltaic maximum power point circuit design, we can save 40.37% transistor count and lower 78.37% power consumption while maintain the same power conversion efficiency of 97.9%. To make the whole system can be used with low-voltage solar cells, we implemented our chip in TSMC 90nmCMOS process with chip area of 1199um*679um.
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I. C. Wey |
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I. C. Wey Cheng Chang Chen 陳政昌 |
author |
Cheng Chang Chen 陳政昌 |
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Cheng Chang Chen 陳政昌 Folded Photovoltaic Maximum Power Point Tracking Chip Design Based on Schedule Reordering Technique and Lookahead Restoring Divider |
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Cheng Chang Chen |
title |
Folded Photovoltaic Maximum Power Point Tracking Chip Design Based on Schedule Reordering Technique and Lookahead Restoring Divider |
title_short |
Folded Photovoltaic Maximum Power Point Tracking Chip Design Based on Schedule Reordering Technique and Lookahead Restoring Divider |
title_full |
Folded Photovoltaic Maximum Power Point Tracking Chip Design Based on Schedule Reordering Technique and Lookahead Restoring Divider |
title_fullStr |
Folded Photovoltaic Maximum Power Point Tracking Chip Design Based on Schedule Reordering Technique and Lookahead Restoring Divider |
title_full_unstemmed |
Folded Photovoltaic Maximum Power Point Tracking Chip Design Based on Schedule Reordering Technique and Lookahead Restoring Divider |
title_sort |
folded photovoltaic maximum power point tracking chip design based on schedule reordering technique and lookahead restoring divider |
publishDate |
2011 |
url |
http://ndltd.ncl.edu.tw/handle/50082500358881037439 |
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