| Summary: | 碩士 === 長庚大學 === 電機工程學系 === 99 === When the technology continuously scaling down, the short channel effects and the presence of the voltage, process, and temperature variations make the circuit hard to design；Delay-Locked Loops (DLLs) have been used for clock deskew in stead of Phase-Locked Loops (PLLs) because of easy design and inherent stable；A clock with 50％ duty cycle is extremely important in many double-rate system such as DDR-SDRAMs and analog-to-digital converters. To acquire the clock phase and to assure the 50％ duty cycle of the clock, it results in the growth of the phase-locked loops (PLLs), delay-locked loops (DLLs), and duty-cycle corrector (DCC).
A DLL-based Pulsewidth Control Loop With Phase Error Corrector is presented in paper. It generates the output clock of 50±1% duty cycle when the input duty cycle clock is within 40% ~ 60% and the phase error is less than 8ps. The circuit is designed and simulated using 1P6M 0.18um CMOS process. The operation frequency range is from 900MHz to 1.1GHz.
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