Multi-Channel-Length Sub-Threshold CMOS Circuits
碩士 === 國立中正大學 === 電機工程研究所 === 99 === There are more special process procedure in nano era which changed the characteristic of semiconductor. The performance and energy consumption will get lost once designer still keep the same design technique without process consideration. A special byproduct call...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/51703095557966187636 |
| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 99 === There are more special process procedure in nano era which changed the characteristic of semiconductor. The performance and energy consumption will get lost once designer still keep the same design technique without process consideration. A special byproduct called reverse short-channel-effect (RSCE) which can improve the circuit performance is involved. This paper will explore the circuit performance by utilizing TSMC 65 nm process.
At present, foundry didn’t provide the special model for sub-threshold circuit design application. It is difficult to design a sub-threshold circuit due to the leakage at the sub-threshold operation. This paper will focus on the nanometer technology circuit design at sub-threshold operation. And design the standard cell library and flip-flops with reverse short-channel-effect (RSCE). This paper is also describe a device size optimization which be considered for sub-threshold operation. Experiment results using ISCAS’2003 benchmarks and fabricated in TSMC 65nm CMOS technology show that the critical path delay, power consumption.
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